Which boards work together to form a three-phase inverter reference design?

The following boards work in tandem to form this three-phase inverter reference design: The UCC21710 device is a 5.7-kVRMS, reinforced isolated gate driver for Insulated-Gate Bipolar Transistors (IGBT) and SiC MOSFETs with split outputs, providing 10-A source and 10-A sink current.

How does a solar hybrid inverter work?

Fight back with the new S6 solar hybrid inverter from Solis. S6 Solar inverter that can connect solar panels and a high voltage battery. This inverter will capture the solar during the day and provide power to your home loads and charge the battery. At night it will use the battery to satisfy your home loads.

How to choose a suitable inverter?

With the thermal impedance information of the thermal system design, the proper device rating can be selected. The 1200-V/75-mΩ SiC MOSFET and 650-V/60-mΩ SiC MOSFET is a good tradeoff among thermal, efficiency and cost. The primary source of lost efficiency in any inverter is going to be a result of the losses incurred in the switching devices.

How does a three-phase AFE converter work?

The design uses switching frequency up to 90kHz and an LCL output filter to reduce the size of the magnetics. A peak efficiency of 98.6% is achieved. The design shows how to implement a complete three-phase AFE control in the DQ domain. This bidirectional converter enables both DC fast charging and vehicle-to-grid (V2G) applications.

What is the peak efficiency of a three-phase AFE converter?

A peak efficiency of 98.6% is achieved. The design shows how to implement a complete three-phase AFE control in the DQ domain. This bidirectional converter enables both DC fast charging and vehicle-to-grid (V2G) applications. Beginning of dialog window. Escape will cancel and close the window. This is a modal window.

What is a T-type 3-level inverter?

The next step up from a standard two-level inverter is a T-type three-level inverter. This type is implemented by inserting two back-to-back switching devices between the switch node and the neutral point of the DC link created by the bulk input capacitors.